`timescale	1ps/1ps
module L9_spi_com_01(
		input	wire		resetb,
		input	wire		sclk,
		input	wire		comm_en,

		//和MCU接口	
		input	wire		mcu_spi_cs,
		input	wire		mcu_spi_clk,
		input	wire		mcu_spi_mosi,
		output	reg		mcu_spi_miso,

		//和PHY接口	
		output	reg		send_flag,
		output	reg		pre_flag,
		output	reg	[7:0]	send_data,
		
		//PHY反馈接口
		input	wire	[31:0]	set_addr,
		input	wire		read_state_req,
		output	reg	[7:0]	rd_data,

		//设备模式
		output	reg		sub_mode,

		//MCU控制输出
		output	reg		mcu_set_d_ok,
		output	reg	[15:0]	mcu_set_addr,
		output	reg	[7:0]	mcu_set_data,

		output	reg		mcu_ext_d_ok,
		output	reg	[15:0]	mcu_ext_addr,

		//状态和反馈数据输入
		input	wire	[7:0]	mcu_rd_data,
		input	wire	[7:0]	fpga_state,
		input	wire	[7:0]	phy_state,
		input	wire	[9:0]	current_depth,
		input	wire	[1:0]	depth_state,
		input	wire	[7:0]	sys_port,

		//和SD卡接口	
		output	reg		mcu_sd_en,

		//和Flash接口	
		output	reg		mcu_flash_en,

		//universe读接口	
		input	wire	[4:0]	universe_r_addr,
		output	wire	[15:0]	universe_r_data,

		//配置输出
		output	reg		artnet_en,
		output	reg	[5:0]	device_port,
		output	wire	[12:0]	port_start,
		
		//调试信号
		output	wire	[7:0]	tout
		);

//**********************************************/
//		信号定义
/***********************************************/
wire	[1:0]	logic_mode;

reg		send_buf_wen;
wire	[10:0]	send_buf_raddr;
wire	[13:0]	send_buf_waddr;
wire		send_buf_wdata;
wire	[7:0]	send_buf_rdata;

reg		mcu_spi_cs_a, mcu_spi_mosi_a, mcu_spi_clk_a;
reg		spi_en, spi_bit_in, spi_clk, spi_en_t, spi_clk_t;
reg		spi_bit_sync, spi_byte_sync, spi_rec_over, spi_rec_end;
wire		data_sync;
reg	[7:0]	data_sync_t;
reg	[13:0]	spi_rec_count;
wire	[10:0]	spi_byte_count;
reg	[7:0]	spi_shift_d, spi_data;
reg		spi_55_flag, spi_phy_flag, reg_write_flag, reg_read_flag, reg_config_flag;
reg	[10:0]	send_phy_max, send_phy_count;
reg		send_phy_flag, send_phy_last, send_phy_flag_t;

reg		reg_write_en, addr_count_en, reg_config_end, ext_flag, state_flag;
reg	[31:0]	reg_base_addr, reg_cfg_addr;
reg	[8:0]	reg_cfg_length;
reg	[7:0]	reg_cfg_data;

reg		spi_mode_flag;
reg	[1:0]	spi_mode;
	
reg	[7:0]	mcu_read_data;
wire	[2:0]	spi_bit_sel;

reg		mode_config_flag;
reg	[7:0]	mode_config;

reg		info_we;
reg	[9:0]	info_addr;
reg	[7:0]	info_wdata;
wire	[7:0]	info_rdata;

reg	[7:0]	info_u_addr;
reg	[3:0]	state_load;
reg	[7:0]	info_state_rdata;
reg		mcu_config_en, mcu_w_req, phy_ack_en;
reg	[7:0]	mcu_w_addr;
reg	[9:0]	port_base;

wire	[7:0]	fpga_state_a;

reg	[7:0]	device_main_type;
reg	[9:0]	cascade_max;
reg	[8:0]	device_base;
reg	[5:0]	occupy_port;
reg		sys_port_en;

//**********************************************/
//		参数定义
/***********************************************/
//程序版本信息
parameter	main_function	=  "S";		//ASCII "S"  
parameter	sub_function	=  "L";		//ASCII "L"  
parameter	main_solution	=  9;		//"9"        
parameter	sub_solution	=  9;		//"09"       
parameter	application_type=  "G";		//ASCII "G"  
parameter	main_version	=  8'd3;	//"03"       
parameter	sub_version	=  8'd8;	//"X01"  
parameter	mini_version	=  8'd1;	//" "  

`ifdef BOOT_MODE
	assign	logic_mode = 3;
`else
	`ifdef TEST_MODE
		assign	logic_mode = 2;
	`else
		assign	logic_mode = 1;
	`endif
`endif
//parameter	LOGIC_MODE	=	3;	//initial

//*************************************************/
//		数据缓冲
//*************************************************/
L9_swsr_16kw1_2kr8_dp	send_buf(
	.wrclock(sclk),
	.wren(send_buf_wen),
	.wraddress(send_buf_waddr),
	.data(send_buf_wdata),
	
	.rdclock(sclk),
	.rdaddress(send_buf_raddr),
	.q(send_buf_rdata)
	);

//***************缓冲控制***************
//send_buf控制信号
always @( * )
	if ((spi_en == 1) && (spi_rec_over == 0))
		send_buf_wen <= spi_bit_sync;
	else
		send_buf_wen <= 0;

assign	send_buf_waddr = {spi_rec_count[13:3], ~spi_rec_count[2:0]};
assign	send_buf_wdata = spi_bit_in;
assign	send_buf_raddr = send_phy_count;

//************************************************/
//		SPI接口处理
//************************************************/
//接口缓冲
always@(posedge sclk) begin
	mcu_spi_cs_a <= ~mcu_spi_cs;
	spi_en <= mcu_spi_cs_a;
	
	mcu_spi_mosi_a <= mcu_spi_mosi;
	spi_bit_in <= mcu_spi_mosi_a;
	
	mcu_spi_clk_a <= mcu_spi_clk;
	spi_clk <= mcu_spi_clk_a;
	end

//信号延迟
always@(posedge sclk) begin
	spi_en_t <= spi_en;
	spi_clk_t <= spi_clk;
	end

//bit数据同步
always@(posedge sclk)
	if ((spi_clk == 1) && (spi_clk_t == 0))
		spi_bit_sync <= 1;
	else
		spi_bit_sync <= 0;
		
//接收计数
always@(posedge sclk)
	if (spi_en == 0)
		spi_rec_count <= 14'h00;
	else if ((spi_bit_sync == 1) && (spi_rec_over == 0))
		spi_rec_count <= spi_rec_count + 1;

//接收长度控制(SPI包长度不大于1920个字节）
always@(posedge sclk)
	if (spi_rec_count[13:10] == 4'b1111)
		spi_rec_over <= 1;
	else
		spi_rec_over <= 0;
		
//数据串入，高位在前
always@(posedge sclk)
	if (spi_bit_sync == 1)
		spi_shift_d <= {spi_shift_d[6:0], spi_bit_in};
		
//btye数据同步
always@(posedge sclk)
	if ((spi_clk == 1) && (spi_clk_t == 0) && (spi_rec_count[2:0] == 3'b111) && (spi_rec_over == 0))
		spi_byte_sync <= 1;
	else
		spi_byte_sync <= 0;
		
//数据锁存
always@(posedge sclk)
	if (spi_byte_sync == 1)
		spi_data <= {spi_shift_d[6:0], spi_bit_in};

//************************************************/
//		SPI类型处理
//************************************************/
//字节计数
assign	spi_byte_count = spi_rec_count[13:3];

//数据同步延时
always@(posedge sclk)
	data_sync_t <= {data_sync_t[6:0], spi_byte_sync};

//数据同步
assign	data_sync = data_sync_t[5];
	
//通讯包标志
always@(posedge sclk or negedge resetb)
	if(resetb == 0)
		spi_55_flag <= 0;
	else if ((data_sync == 1) && (spi_byte_count == 1)) begin
		if (spi_data == 8'h55)
			spi_55_flag <= 1;
		else
			spi_55_flag <= 0;
		end
	
//网口通讯包标志
always@(posedge sclk)
	if ((data_sync == 1) && (spi_byte_count == 2)) begin
		if ((spi_55_flag == 1) && (spi_data == 8'h55))
			spi_phy_flag <= 1;
		else
			spi_phy_flag <= 0;
		end

//寄存器写通讯包标志
always@(posedge sclk)
	if ((data_sync == 1) && (spi_byte_count == 2)) begin
		if ((spi_55_flag == 1) && (spi_data == 8'h5A))
			reg_write_flag <= 1;
		else
			reg_write_flag <= 0;
		end

//寄存器读通讯包标志
always@(posedge sclk)
	if ((data_sync == 1) && (spi_byte_count == 2)) begin
		if ((spi_55_flag == 1) && (spi_data == 8'h33))
			reg_read_flag <= 1;
		else
			reg_read_flag <= 0;
		end

//寄存器读写通讯包标志
always@(posedge sclk)
	if ((reg_write_flag == 1) || (reg_read_flag == 1))
		reg_config_flag <= 1;
	else
		reg_config_flag <= 0;

//************************************************/
//		网口转发处理
//************************************************/
//接收结束标志
always@(posedge sclk)
	if ((spi_en == 0) && (spi_en_t == 1))
		spi_rec_end <= 1;
	else
		spi_rec_end <= 0;
		
//保存转发长度
always@(posedge sclk or negedge resetb)
	if (resetb == 0)
		send_phy_max <= 8;		//初始化非0，防止产生错误的send_phy_last
	else if ((spi_en == 0) && (spi_en_t == 1)) begin
		if (spi_byte_count > 18)
			send_phy_max <= spi_byte_count - 2;
		else
			send_phy_max <= 8;
		end

//PHY转发使能
always@(posedge sclk or negedge resetb)
	if (resetb == 0)
		send_phy_flag <= 0;
	else if ((spi_rec_end == 1) && (spi_phy_flag == 1) && (send_phy_max > 16))
		send_phy_flag <= 1;
	else if (send_phy_last == 1)
		send_phy_flag <= 0;

//PHY转发计数
always@(posedge sclk)
	if (send_phy_flag == 0)
		send_phy_count <= 0;
	else
		send_phy_count <= send_phy_count + 1;

//PHY转发结束
always@(posedge sclk)
	if ((send_phy_flag == 1) && (send_phy_count >= send_phy_max))
		send_phy_last <= 1;
	else
		send_phy_last <= 0;

//***************输出给PHY的信号***************
//MCU应答信号
always@(posedge sclk) begin
	send_phy_flag_t <= send_phy_flag;
	send_flag <= send_phy_flag_t;
	end

always@(posedge sclk)
	if (send_phy_count > 0 && send_phy_count < 9)
		pre_flag <= 1;
	else
		pre_flag <= 0;

always@(posedge sclk)
	if (send_phy_flag_t == 1)
		send_data <= send_buf_rdata;
	else
		send_data <= 0;

//************************************************/
//		参数设置处理
//************************************************/
always@(posedge sclk or negedge resetb)
	if(resetb == 0) begin
		reg_base_addr <= 0;
		reg_cfg_length <= 0;
		end
	else if ((data_sync == 1) && (reg_config_flag == 1))
		case (spi_byte_count)
			3:	reg_base_addr[7:0] <= spi_shift_d;
			4:	reg_base_addr[15:8] <= spi_shift_d;
			5:	reg_base_addr[23:16] <= spi_shift_d;
			6:	reg_base_addr[31:24] <= spi_shift_d;
			7:	reg_cfg_length[7:0] <= spi_shift_d;
			8:	reg_cfg_length[8] <= spi_shift_d[0];
		endcase

always@(posedge sclk)
	if (spi_byte_count >= (reg_cfg_length + 8))
		reg_config_end <= 1;
	else
		reg_config_end <= 0;
		
always@(posedge sclk or negedge resetb)
	if(resetb == 0)
		addr_count_en <= 0;
	else if ((spi_en == 0) || (spi_rec_over == 1))
		addr_count_en <= 0;
	else if (data_sync == 1) begin
		if (reg_config_end == 1)
			addr_count_en <= 0;
		else if ((reg_write_flag == 1) && (spi_byte_count >= 9))
			addr_count_en <= 1;
		else if ((reg_read_flag == 1) && (spi_byte_count >= 7))
			addr_count_en <= 1;
		else
			addr_count_en <= 0;
		end
		
always@(posedge sclk or negedge resetb)
	if(resetb == 0)
		reg_write_en <= 0;
	else if ((spi_en == 0) || (spi_rec_over == 1))
		reg_write_en <= 0;
	else if (data_sync == 1) begin
		if (reg_config_end == 1)
			reg_write_en <= 0;
		else if ((reg_write_flag == 1) && (spi_byte_count >= 8))
			reg_write_en <= 1;
		else
			reg_write_en <= 0;
		end
		
always@(posedge sclk)
	if (spi_byte_sync == 1) begin
		if (addr_count_en == 0)
			reg_cfg_addr <= reg_base_addr;
		else
			reg_cfg_addr <= reg_cfg_addr + 1;
		end
	
always@( * ) begin
	mcu_set_addr <= reg_cfg_addr[15:0];
	mcu_ext_addr <= reg_cfg_addr[31:16];
	mcu_set_data <= spi_data;
	end

always@(posedge sclk)
	if (mcu_ext_addr == 16'h0)
		ext_flag <= 0;
	else
		ext_flag <= 1;

reg		w_d_ok;
reg	[7:0]	w_d_ok_t;

always@(posedge sclk)
	if ((reg_write_flag == 1) && (data_sync == 1) && (reg_write_en == 1))
		w_d_ok <= 1;
	else
		w_d_ok <= 0;
		
always@(posedge sclk)
	w_d_ok_t <= {w_d_ok_t, w_d_ok};
		
always@(posedge sclk)
	if ((w_d_ok_t == 1) && (ext_flag == 0))
		mcu_set_d_ok <= 1;
	else
		mcu_set_d_ok <= 0;
		
always@(posedge sclk)
	if ((w_d_ok_t == 1) && (ext_flag == 1))
		mcu_ext_d_ok <= 1;
	else
		mcu_ext_d_ok <= 0;
	
//***********************************************/
//		参数读取处理
//***********************************************/
//返回数据bit选择
always@(posedge sclk)
	if (reg_cfg_addr[31:8] == 24'h000000)
		state_flag <= 1;
	else
		state_flag <= 0;
	
//返回数据
always@(posedge sclk)
	if (reg_read_flag == 0)
		mcu_read_data <= 0;
	else if (spi_byte_sync == 1) begin
		if (addr_count_en == 0)
			mcu_read_data <= 0;
		else if (state_flag == 1)
			case (mcu_set_addr[7:0])
				8'h00:	mcu_read_data <= fpga_state;
				8'h01:	mcu_read_data <= 8'h55;//fpga_state[0];//fpga_state
				8'h02:	mcu_read_data <= "H";
				8'h07:	mcu_read_data <= phy_state;
				8'h08:	mcu_read_data <= current_depth[7:0];
				8'h09:	mcu_read_data <= current_depth[9:8];
				8'h0A:	mcu_read_data <= fpga_state_a;
				8'h0B:	mcu_read_data <= occupy_port;
				8'h0F:	mcu_read_data <= logic_mode;
				8'h10:	mcu_read_data <= main_function;
				8'h11:	mcu_read_data <= sub_function;
				8'h12:	mcu_read_data <= main_solution;
				8'h13:	mcu_read_data <= sub_solution;
				8'h14:	mcu_read_data <= application_type;
				8'h15:	mcu_read_data <= main_version;
				8'h16:	mcu_read_data <= sub_version;
				8'h17:	mcu_read_data <= mini_version;
				
				default:	mcu_read_data <= mcu_rd_data;
			endcase
		else
			mcu_read_data <= mcu_rd_data;
		end

//返回数据bit选择
assign	spi_bit_sel = ~spi_rec_count;
	
//返回数据
always@(posedge sclk)
	mcu_spi_miso <= mcu_read_data[spi_bit_sel];

//************************************************/
//		工作模式处理
//************************************************/
always@(posedge sclk)
	if((mcu_ext_addr == 16'h0001) && (mcu_set_addr[15:8] == 8'h01))	
		mode_config_flag <= 1;
	else
		mode_config_flag <= 0;

always@(posedge sclk or negedge resetb)
	if(resetb == 0)		
		mode_config <= 0;
	else if ((mcu_ext_d_ok == 1) && (mode_config_flag == 1) && (mcu_set_addr[7:0] == 8'h00))
		mode_config <= mcu_set_data;

always@(posedge sclk or negedge resetb)
	if(resetb == 0)
		mcu_sd_en <= 0;
	else if ((mcu_ext_d_ok == 1) && (mode_config_flag == 1) && (mcu_set_addr[7:0] == 8'h01)) begin
		if ((mode_config == 8'h35) && (mcu_set_data == 8'hCA))
			mcu_sd_en <= 1;
		else
			mcu_sd_en <= 0;
		end
	
always@(posedge sclk or negedge resetb)
	if(resetb == 0)
		mcu_flash_en <= 0;
	else if ((mcu_ext_d_ok == 1) && (mode_config_flag == 1) && (mcu_set_addr[7:0] == 8'h01)) begin
		if ((mode_config == 8'hAD) && (mcu_set_data == 8'h52))
			mcu_flash_en <= 1;
		else
			mcu_flash_en <= 0;
		end
	
//************************************************/
//		MCU<->PHY缓冲
//************************************************/
//数据交换缓冲区
L9_swsr_1k8_512X16_tdp info_buf(
	.clock_a(sclk),
	.wren_a(info_we),
	.address_a(info_addr),
	.data_a(mcu_set_data),
	.q_a(info_rdata),
	
	.clock_b(sclk),
	.wren_b(1'b0),
	.address_b({2'b11, info_u_addr}),
	.data_b(0),
	.q_b(universe_r_data));

//端口A控制选通
always	@(posedge sclk)
	if (mcu_w_req == 1) begin
		info_we <= 1'b1;
		info_addr <= {2'b11, mcu_w_addr};
		end
	else begin
		info_we <= 1'b0;
		info_addr <= {2'b11, set_addr[7:0]};
		end

//PHY反馈数据加载
always	@(posedge sclk)
	state_load <= {state_load[2:0], ~info_we};

always	@(posedge sclk)
	if (state_load[1] == 1)
		info_state_rdata <= info_rdata;

//universe读取地址
always	@(posedge sclk)
	info_u_addr <= universe_r_addr + 7'h28;

//************************************************/
//		设备模式配置
//************************************************/
//MCU设置使能
always	@(posedge sclk)
	if (mcu_ext_addr == 16'h0001)
		mcu_config_en <= 1;
	else
		mcu_config_en <= 0;

//写入info_buf请求
always	@(posedge sclk)
	if (mcu_config_en == 0)
		mcu_w_req <= 0;
	else if ((mcu_set_addr[15:0] >= 16'h2100) && (mcu_set_addr[15:0] <= 16'h210B))	//设备型号
		mcu_w_req <= 0;
	else if (mcu_ext_d_ok == 1)
		mcu_w_req <= 1;
	else if (read_state_req == 0)
		mcu_w_req <= 0;

//写入info_buf地址
always	@(posedge sclk)
	if (mcu_config_en == 0)
		mcu_w_addr	<=8'h0;
	else if ((mcu_set_addr[15:0] >= 16'h2100) && (mcu_set_addr[15:0] <= 16'h210B))	//设备型号
		mcu_w_addr <= {4'h1, mcu_set_addr[3:0]};
	else if ((mcu_set_addr[15:0] >= 16'h2120) && (mcu_set_addr[15:0] <= 16'h212F))	//单片机版本号
		mcu_w_addr <= {4'h2, mcu_set_addr[3:0]};
	else if ((mcu_set_addr[15:0] >= 16'h2130) && (mcu_set_addr[15:0] <= 16'h213B))	//生产序号
		mcu_w_addr <= {4'hF, mcu_set_addr[3:0]};
	else if ((mcu_set_addr[15:0] >= 16'h2200) && (mcu_set_addr[15:0] <= 16'h220F))	//端口序号0~7
		mcu_w_addr <= {4'h5, mcu_set_addr[3:0]};
	else if ((mcu_set_addr[15:0] >= 16'h2210) && (mcu_set_addr[15:0] <= 16'h221F))	//端口序号8~15
		mcu_w_addr <= {4'h6, mcu_set_addr[3:0]};
	else if ((mcu_set_addr[15:0] >= 16'h2240) && (mcu_set_addr[15:0] <= 16'h224F))	//端口状态0~7
		mcu_w_addr <= {4'h9, mcu_set_addr[3:0]};
	else if ((mcu_set_addr[15:0] >= 16'h2250) && (mcu_set_addr[15:0] <= 16'h225F))	//端口状态8~15
		mcu_w_addr <= {4'hA, mcu_set_addr[3:0]};
	else
		case (mcu_set_addr)
			16'h0400:	mcu_w_addr	<=8'h0C;			//灯具检测状态
			16'h2110:	mcu_w_addr	<=8'h32;			//设备级联限制
			16'h2111:	mcu_w_addr	<=8'h33;			//设备级联限制
			16'h2114:	mcu_w_addr	<=8'h0D;			//设备端口数
			default:	mcu_w_addr	<=8'h0;
		endcase

//设备参数配置
always	@(posedge sclk or negedge resetb)
	if (resetb==0) begin
		device_main_type <= "H";
		cascade_max <= 512;
		device_port <= 8;
		end
	else if ((mcu_ext_d_ok == 1) && (mcu_config_en == 1))
		case (mcu_set_addr)
//			16'h2100:	device_main_type[7:0]	<= mcu_set_data;	//设备主类型
			16'h2110:	cascade_max[7:0]	<= mcu_set_data;	//设备级联限制
			16'h2111:	cascade_max[9:8]	<= mcu_set_data[1:0];	//设备级联限制
			16'h2113:	artnet_en 		<= mcu_set_data[0];	//artnet模式使能
			16'h2114:	device_port		<= mcu_set_data;	//设备端口数
		endcase

//分控模式判断
always@(posedge sclk or negedge resetb)
//	if (resetb == 0)
//		sub_mode <= 1;
//	else if ((mcu_ext_d_ok == 1) && (mcu_config_en == 1) && (mcu_set_addr[15:0] == 16'h2250) && (mcu_set_data == "M"))
		sub_mode <= 0;
//	else
//		sub_mode <= 1;

//************************************************/
//		设备模式网口反馈
//************************************************/
//网口反馈使能
always	@(posedge sclk)
	if (set_addr[31:8] == 24'h000000)
		phy_ack_en <= 1'b1;
	else
		phy_ack_en <= 1'b0;

//反馈数据选通
always	@(posedge sclk)
	if (phy_ack_en == 1'b0)
		rd_data <= 8'h00;
	else if ((set_addr[7:0] >= 8'h10) && (set_addr[7:0] <= 8'h1B))	//设备型号
		rd_data <= info_state_rdata;
	else if ((set_addr[7:0] >= 8'h20) && (set_addr[7:0] <= 8'h2F))	//单片机版本号
		rd_data <= info_state_rdata;
	else if ((set_addr[7:0] >= 8'h50) && (set_addr[7:0] <= 8'h6F))	//端口universe号
		rd_data <= info_state_rdata;
	else if ((set_addr[7:0] >= 8'h90) && (set_addr[7:0] <= 8'hAF))	//端口状态
		rd_data <= info_state_rdata;
	else if ((set_addr[7:0] >= 8'hF0) && (set_addr[7:0] <= 8'hFB))	//设备序号
		rd_data <= info_state_rdata;
	else
		case (set_addr[7:0])
			8'h06:	rd_data	<= phy_state;			//网口通讯状态
			8'h0c:	rd_data <= info_state_rdata;		//灯具检测状态
			8'h0d:	rd_data <= info_state_rdata;		//设备有效端口数
			8'h0e:	rd_data <= occupy_port;			//设备占用端口数
			8'h0f:	rd_data <= fpga_state;			//设备工作状态
			8'h30:	rd_data <= fpga_state_a;		//级联&端口状态
			8'h32:	rd_data <= info_state_rdata;		//设备级联限制
			8'h33:	rd_data <= info_state_rdata;		//设备级联限制
			default:	rd_data <= 8'h00;
		endcase

//************************************************/
//		设备工作状态
//************************************************/
assign	fpga_state_a = {sys_port_en, depth_state};

//系统设备占用端口数使能
always	@(posedge sclk)
	if (sys_port == 0)
		sys_port_en <= 0;
	else
		sys_port_en <= 1;

//设备占用端口数
always	@(posedge sclk)
	if (sys_port_en == 0)
		occupy_port <= device_port;
	else
		occupy_port <= sys_port;

//设备号
always	@(posedge sclk)
	if (current_depth < cascade_max)
		device_base <= current_depth - 1;
	else
		device_base <= cascade_max - 1;

//起始端口计算
L9_mult_9X9_sync port_mult(
	.clock(sclk),
	.dataa(device_base),
	.datab(occupy_port),
	.result(port_start)
	);

/************************************************/
//		测试信号
/************************************************/
assign	tout = {spi_en, spi_bit_in, spi_clk, spi_bit_sync, spi_byte_count[0], spi_mode_flag};

endmodule		
